The present invention is related to a monolithic multi-layer capacitor comprising an improved lead-out structure. More specifically, the present invention is related to a capacitor wherein internal electrode plates comprise lead-out electrodes with minimal contribution to equivalent series inductance (ESL).
There has been an ongoing desire for generations to continue the miniaturization of electronic components. Each generation of electronic component allows a higher density of mounted components on a circuit board, or other support, which thereby allows miniaturization of the entire apparatus. As components become smaller, and more closely arranged, cumulative effects began to emerge which previously were of no concern. One such cumulative effect is inductance.
Any flowing current has associated therewith a magnetic field. It is well known that capacitors, particularly multi-layer capacitors, have an equivalent series inductance due, in part, to the current flowing through the lead-out electrodes. There have been many approaches in the art to solving this problem.
The predominant approach to lowering inductance in a capacitor body has been based on the well known physical laws which describe inductance as proportional to length and inversely proportional to width of the charge carrying structure. For example, Naito et al., in U.S. Pat. No. 6,226,169, has defined the aspect ratio, or length divided by width, of lead-out electrodes to be less than 3.0. This approach is limited in the improvement that can be obtained since the advantages are quickly mitigated by structural limitations within the capacitor. Lowering the aspect ratio by widening the lead-out electrodes limits how close the external electrodes can be placed. Lowering the aspect ratio by decreasing the length is limited by the separation between the external electrode and the land of the opposite polarity internal electrode.
Yet another common approach is based on the cancellation, instead of elimination, of inductance. A myriad of examples are available in the art wherein the lead-out electrodes are oriented such that current in adjacent lead-out electrodes is countered thereby cancelling inductance. This approach has met with limited success and as further miniaturization is sought this approach is found to be insufficient. One potential problem is the naturally occurring manufacturing deviations. Capacitors cannot be made that perfectly balance out the current flow to negate ESL. In theory, this technique could provide a capacitor with virtually no ESL however in practice the technique is limited by manufacturing tolerance realities. As further minimization is desired the manufacturing tolerances become even more critical thereby further limiting the ability of cancellation techniques.
Those skilled in the art have been limited to lowering the ESL by lowering the aspect ratio, which is bound by physical constraints, or by cancellation effects, which are bound by manufacturing tolerances. There has yet to be a solution to the reduction in ESL suitable to allow further minimization in capacitors.